Transistors in an integrated circuit have critical performance parameters that have statistical distributions around nominal values caused for example by variability of manufacturing steps. For a particular fabrication process, a foundry typically specifies to designers information about these nominal values and variability. If a chip is designed to work properly only if the nominal values are achieved in a particular manufactured device, then as many as half the manufactured devices will not work. Designers therefore have to design their circuits to a specification that is some amount inferior to the specified nominal values to account for device variability.
Commonly, foundries describe variability of a parameter by assuming it conforms to a Gaussian distribution. The actual distribution may not be exactly Gaussian, but a Gaussian distribution is usually presumed. Such a distribution is characterized by a mean and a standard deviation, where the value of a standard deviation of a parameter from the nominal value is a measure of that parameter's variability. Circuit designers often design their chips to function properly should any critical parameter of a manufactured chip be up to 3 standard deviations inferior to the specified nominal value; so the design target is nominal performance minus three times the standard deviation (also called “3 sigmas”). Manufactured chips that do not meet this 3 sigma window may be discarded.
With the upcoming transition from FinFETs to nanowire transistors, transistor variability is expected to increase, which means that the value of sigma will increase. Thus the 3 sigma margin will also increase, forcing designers to design their chips to a specification that is significantly below the foundry's specified nominal performance parameters. Such wide variabilities also make electronic design automation for high performance integrated circuits more complex.